The present invention relates to a sense-amplifying circuit for detecting and amplifying slight differential signals in a semiconductor circuit.
Conventionally, a circuit as shown in FIG. 6(a), FIG. 7(a) or FIG. 7(b) is used as a sense-amplifying circuit in a semiconductor device. In the drawings, TPn wherein n represents an integer of 0 or more and TNn wherein n represents an integer of 0 or more indicate a p-channel metal oxide semiconductor (hereinafter referred to as p-MOS) transistor and a n-channel metal oxide semiconductor (hereinafter referred to as a n-MOS) transistor, respectively. A sense-amplifying circuit 60 shown in FIG. 6(a) is an amplifier wherein two sense-amplifying circuits 90 using a current-mirror load shown in FIG. 6(b) is symmetrically arranged in parallel, and is widely used for a high-speed complementary metal oxide semiconductorxe2x80x94static random access memory (hereinafter referred to as CMOS-SRAM). Further, the sense-amplifying circuit 60 is experimentally used as a read amplifier of a dynamic random access memory (hereinafter referred to as DRAM). A sense-amplifying circuit 70 shown in FIG. 7(a) is an improved type of the sense-amplifying circuit 60 shown in FIG. 6(a), wherein gain is improved by adding p-MOS transistors QP1 to QP4 as active loads to said circuit 60. A sense-amplifying circuit 80 shown in FIG. 7(b) is generally used for amplifying bit line signals of a CMOS-DRAM, and can be used for a static random access memory (hereinafter referred to as SRAM).
In the sense-amplifying circuits 60 and 70 of FIGS. 6(a) and 7(a), however, the output signals D and D-bar (which is an inverted signal of the signal D) are not amplified up to the power source level (VDD) and the ground level (VSS). Therefore, it is necessary to provide another amplifier or further amplifiers in a subsequent stage. Further, since through current flows even after amplification, power-saving can hardly be achieved. If another circuit is provided in the subsequent stage, input level of this circuit is of medium electric potential. Therefore, through current flows at least in an input part of the amplifying circuit in the subsequent stage while the amplifying circuit is active. Thus, power-saving is more difficult to be achieved. Further, the sense-amplifying circuits shown in FIG. 6(a) and FIG. 7(a) each have a number of transistors and thus occupy large area on the chip. Considering the amplifying circuit in the subsequent stage, larger area on the chip is occupied by the two circuits.
A sense-amplifying circuit 80 shown in FIG. 7(b) does not have the above-cited disadvantages, but since output line (input/output lines 82 and 84) are bit lines with a heavy load, much time is needed for amplification. Further, since the sense-amplifying circuit 80 sends input and output signals via common line, even when the circuit 80 is used for a SRAM or a read-only memory (hereinafter referred to as ROM) whose input signals may remain small, input signals are amplified extensively to power source level (VDD) and ground level (VSS). However, since an input line is a bit line which bears heavy capacitive load in most semiconductor memory devices, much power is wasted to charge and discharge the input line (input/output lines 82 and 84).
A sense amplifier capable of lowering power consumption by blocking a flow of through current is disclosed in the Japanese Patent Publication No. 2738306. The sense-amplifying amplifying circuit disclosed in the above publication comprises: a pair of CMOS inverters wherein input and output lines of each inverter are crossed; a power switch NMOS 7 placed between the pair of CMOS inverters and the ground, which is turned ON at the time of sensing; a pull-down nMOS 6 for equalizing each electric potential of output signals of inverters with the ground level before the start of sensing; and a pair of PMOS transistors (Y-selectors 4) connected to the sources of pMOS transistors making up said pair of CMOS inverters. The pair of PMOS transistors selects a pair of differential wires (a pair of bit lines 3), which is turned ON at the time of sensing and is charged up to power voltage level VDD by load PMOS 1.
In the above-cited sense-amplifying circuit, while Y-selectors 4 are turned OFF before the start of sensing operation and a pair of bit lines 3 is charged up to the supply-voltage-level VDD, a pair of data-lines 5 is equalized with the ground level by the pull-down nMOS 6. When the Y-selectors 4 are turned OFF, no through current flows. Then, when a certain potential difference is generated in said pair of bit lines 3, the power-switch 7 is turned ON, the pull-down nMOS 6 is turned OFF less than and either of the above Y-selectors 4 is turned ON. Then, either of said pair of data lines 5 goes H-level to complete reading operation. After completing sensing operation, current is automatically shut off by a characteristic of the CMOS inverter. In consequence, power consumption can be lowered since through current does not flow.
However, in the above-cited sense-amplifying circuit, it is necessary that driving of the output signal of the sense amplifier to the H-level should be executed through the load MOS 1, the selector MOS (Y-selector) 4, and a pull-up device of the sense amplifier. Further, the sense amplifier initially outputs an L-level signal. Consequently, driving force to the H-level is rather weak, and if a pair of bit lines 3 is not precharged to powersource potential, amplification is retarded, and thus it causes a problem. Further, if the selectors MOS (Y-selectors) 4 are turned OFF after amplification, the sense amplifier is disengaged from the power source, and thus the output signal is not retained by a static circuit, but it is retained by a dynamic latch circuit. Therefore, it is quite impossible to preserve data for a long period of time. Even when data is to be preserved for a short period of time, it is possible that the output signal is inverted by lead current and noise.
To remove the above disadvantages, we have eventually found the present invention. An object of the present invention is to provide a small-sized sense amplifier, which is characterized by high-speed operation, minimum power consumption, and capability to amplify input signals rail-to-rail in a single stage.
An essential part of the present invention is to a sense-amplifying circuit comprises:
a pair of inverters wherein an output of each inverter is connected to an input of the other inverter; and
sensing transistors whose drains are respectively connected to the sources of the pair of inverters, whose gates are connected to the sources of the pair of inverters, whose gates are connected to differential input signal lines, and whose sources are mutually connected as a common node.